Research Interests

Energy-Efficient AI Through Bio-Inspired Computing

As artificial intelligence becomes increasingly central to modern technology, its energy demands have grown dramatically—training large AI models can consume as much electricity as several homes use in a year. My research addresses this challenge by developing energy-efficient AI hardware through bio-inspired computer architecture, targeting two interrelated thrusts: 1) brain-inspired computing for resource-constrained systems and 2) high-performance and adaptable computing architectures for emerging AI systems.

My work focuses on developing specialized hardware architectures for brain-inspired computing, with particular emphasis on spiking neural network (SNN) accelerators. Traditional processors struggle with power efficiency when handling AI workloads; SNNs offer a promising alternative by mimicking how biological neural networks process information—using discrete spikes rather than continuous values, enabling dramatically lower power consumption.

I also investigate domain-specific AI accelerators tailored to the unique workload characteristics of SNNs and other applications, alongside dynamically adaptable memory systems that optimize data flow and minimize energy consumption. This research aims to create energy-efficient and scalable AI systems for applications including embedded systems, biomedical devices, autonomous vehicles, and the Internet of Things (IoT).

Why This Matters

AI's energy consumption is growing at an unsustainable rate. Data centers already account for roughly 1-2% of global electricity use, and this figure is climbing as AI models grow larger. Brain-inspired computing offers a path toward sustainable AI by fundamentally rethinking how we design hardware, potentially reducing energy consumption by orders of magnitude while maintaining performance.

Below, I provide a brief overview of my research interests and projects. Selected publications are listed for each area; additional publications can be found on the publications page.

Brain-Inspired AI: SNN Accelerators and In-Memory Computing

While modern AI draws loose conceptual inspiration from the brain, most systems, such as deep learning, transformers, and large language models, operate nothing like biological neural networks. My research pursues a different approach: brain-inspired computing, which replicates how the brain actually processes information through spike-based communication, temporal coding, and event-driven processing.

This work draws inspiration from the brain's remarkable computational efficiency. The human brain consumes roughly 20 watts while effortlessly performing complex cognitive tasks that even advanced AI systems struggle to match—often requiring kilowatts of power for similar results. This thousand-fold efficiency gap motivates my exploration of brain-inspired hardware/software co-design strategies, particularly for resource-constrained AI systems.

To bridge the divide between biological and artificial intelligence, I investigate how principles like hierarchical encoding, sparsity, and noise tolerance can transform AI computing paradigms and reduce energy consumption.

Specifically, my lab focuses on understanding and replicating the brain's sparse coding mechanisms within SNNs, enhancing their efficiency when accelerated in hardware. We develop tools and methodologies tailored to the temporal dynamics of SNNs, optimizing accelerator designs for both speed and energy efficiency. Additionally, I explore how emerging memory technologies—including spin-transfer torque RAM (STT-RAM) and antiferromagnetic tunnel junctions (AFMTJ)—can enable in-memory and neuromorphic computing designs that process data where it is stored, drawing inspiration from the brain's integrated memory and processing architecture.

Selected Publications

Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study
Yousuf Choudhary and Tosiron Adegbija
Design Automation and Test in Europe (DATE), April 2026
Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture
Ilkin Aliyev, Jesus Lopez, and Tosiron Adegbija
Design Automation and Test in Europe (DATE), March 2025
[Preprint]
PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
Ilkin Aliyev and Tosiron Adegbija
IEEE International Symposium on Circuits and Systems (ISCAS), May 2024
[Preprint]
Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators
Ilkin Aliyev, Kama Svoboda, and Tosiron Adegbija
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), October 2023
[PDF] [URL]
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy
Dhruv Gajaria, Kevin Gomez, and Tosiron Adegbija
IEEE International Conference on Computer Design (ICCD), October 2022
[PDF]

Advancing STTRAM Caches for Runtime Adaptable and Energy-Efficient Microarchitectures (CAREER Project)

On-chip caches are important due to their substantial impact on the energy consumption and performance of a wide variety of computer systems, including desktop computers, embedded systems, mobile devices, servers, etc. As an alternative to traditional static random-access memory (SRAM) for implementing caches, the spin-transfer torque RAM (STTRAM) is a type of non-volatile memory that promises several advantages, such as high density, low leakage, high endurance, and compatibility with complementary metal-oxide-semiconductor (CMOS). However, STTRAM caches still face critical challenges that impede their widespread adoption, such as high write latency and energy. In addition, users of computer systems and the programs that run on the systems typically have variable resource requirements, necessitating caches that can dynamically adapt to runtime needs.

This project investigates several interrelated research problems, including: STTRAM's characteristics and how they can be leveraged for improving the energy efficiency and performance of computer systems that run diverse programs; techniques for improving the user's experience while running the programs; new architectures and management techniques for enabling STTRAM caches that are energy-efficient and can dynamically adapt to running programs' individual needs; and novel methods to address the challenges of implementing STTRAM caches in complex multicore computer systems. Ultimately, the project will develop STTRAM cache architectures that can automatically adapt to the execution needs of diverse programs, resulting in more energy-efficient and faster computer systems.

The project's broader impacts include architectures and methods that will improve the performance and energy efficiency of a wide variety of computer systems for running a wide variety of programs. With the growth of the Internet of Things (IoT), spanning diverse computing and user needs, this project represents an important and necessary step towards adaptable and low-overhead computer systems.

Selected Publications

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches
Kyle Kuan and Tosiron Adegbija
IEEE International Conference on Computer Design (ICCD), October 2020.
[PDF]
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
Kyle Kuan and Tosiron Adegbija
IEEE Transactions on Computers (TC)
[PDF] [URL] [Modified GEM5]
LARS: Logically Adaptable Retention Time STT-RAM Cache for Embedded Systems
Kyle Kuan and Tosiron Adegbija
Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2018.
[PDF] [Modified GEM5]

Domain-Specific Architectures for Resource-Constrained Systems

Ultra-low energy computing is an important requirement for embedded computing platforms used in several domains like wearables, distributed sensing, Intenet of Things, healthcare monitoring. Despite the stringent resource constraints of these systems, the computational demands on them keep rising and their target workloads are increasingly highly dynamic. Furthermore, traditional computer architecture optimization techniques (e.g., complex branch prediction, out-of-order execution, multicore execution) are either over-provisioned or prohibitively overhead-prone for these resource-constrained systems. These challenges necessitate design paradigms that support the variable computing needs of these systems within the limits of their resource constraints.

Domain-specific architectures (DSAs) represent an important direction for enabling low-overhead resource-constrained computing. The main idea of DSAs is to do just a few tasks extremely well. Unlike an application-specific integrated circuit (ASIC), a DSA is tailored to the execution characteristics of a domain of applications, e.g., wearable workloads or automotive applications. This project explores DSAs (including accelerators) for various resource-constrained application domains, to satisfy their unique processing needs, while introducing minimal overhead. Ultimately, this project aims to develop and demonstrate novel repeatable methodologies and domain primitives for identifying domain tasks (unique computing requirements) and designing highly efficient, specialized, and flexible computing architectures for the domain.

Selected Publications

DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing
Ankur Limaye and Tosiron Adegbija
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2021
[PDF]
Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing
Dhruv Gajaria and Tosiron Adegbija
Springer Journal of Signal Processing Systems, July 2021
[PDF] [URL]
ECG-based Authentication using Timing-Aware Domain-Specific Architecture
Renato Cordeiro, Dhruv Gajaria, Ankur Limaye, Tosiron Adegbija, Nima Karimian, and Fatemeh Tehranipoor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)/CODES+ISSS, September 2020
[PDF] [URL]

Microprocessor Optimizations for the Internet of Things (IoT)

The Internet of Things (IoT), which promises to transform the way we live, work, and do business, refers to a pervasive presence of interconnected and uniquely identifiable physical devices. The goal of the IoT is to gather data and drive actions in order to improve productivity and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation, and use. This project explores several facets of designing new, efficient, and adaptable computing architectures for the IoT, broadly divided into: workload characterization of emerging applications and computing for energy-efficient resource-constrained IoT computing.

Selected Publications

Right-Provisioned IoT Edge Computing: An Overview
Tosiron Adegbija, Roman Lysecky, and Vinu Vijay Kumar
ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington DC, USA, May 2019
[PDF]
HERMIT: A Benchmark Suite for the Internet of Medical Things
Ankur Limaye and Tosiron Adegbija
IEEE Internet of Things Journal, 2018.
[PDF] [Download benchmarks]
Microprocessor Optimizations for the Internet of Things: A Survey
Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, and Ann Gordon-Ross
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Special Issue on Circuit and System Design Automation for the Internet of Things, June 2017
[PDF] [URL]