Publications

2026

• Spiking Neural Network Architecture Search: A Survey
  Kama Svoboda and Tosiron Adegbija
  IEEE Computational Intelligence Magazine (CIM), 2026
  [Preprint]

  Abstract

  This survey paper presents a comprehensive examination of Spiking Neural Network (SNN) architecture search (SNNaS) from a unique hardware/software co-design perspective. SNNs, inspired by biological neurons, have emerged as a promising approach to neuromorphic computing. They offer significant advantages in terms of power efficiency and real-time resource-constrained processing, making them ideal for edge computing and IoT applications. However, designing optimal SNN architectures poses significant challenges, due to their inherent complexity (e.g., with respect to training) and the interplay between hardware constraints and SNN models. We begin by providing an overview of SNNs, emphasizing their operational principles and key distinctions from traditional artificial neural networks (ANNs). We then provide a brief overview of the state of the art in NAS for ANNs, highlighting the challenges of directly applying these approaches to SNNs. We then survey the state-of-the-art in SNN-specific NAS approaches. Finally, we conclude with insights into future research directions for SNN research, emphasizing the potential of hardware/software co-design in unlocking the full capabilities of SNNs. This survey aims to serve as a valuable resource for researchers and practitioners in the field, offering a holistic view of SNNaS and underscoring the importance of a co-design approach to harness the true potential of neuromorphic computing.

• Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
  Yuchao Liao, Tosiron Adegbija, and Roman Lysecky
  International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, April 2026
  

  Abstract

  Post-quantum cryptography (PQC) is crucial for securing data against emerging quantum threats. However, its algorithms are computationally complex and difficult to implement efficiently on hardware. In this paper, we explore the potential of Large Language Models (LLMs) to accelerate the hardware-software co-design process for PQC, with a focus on the FALCON digital signature scheme. We present a novel framework that leverages LLMs to analyze PQC algorithms, identify performance-critical components, and generate candidate hardware descriptions for FPGA implementation. We present the first quantitative comparison between LLM-guided synthesis and conventional HLS-based approaches for low-level compute-intensive kernels in FALCON, showing that human-in-the-loop LLM-generated accelerators can achieve up to 2.5x speedup in kernel execution time with significantly fewer cycles, while highlighting trade-offs in resource utilization and power consumption. Our results suggest that LLMs can minimize design effort and development time by automating FPGA accelerator design iterations for PQC algorithms, offering a promising new direction for rapid and adaptive PQC accelerator design on FPGAs.

• Device-Circuit Co-Design of Variation-Resilient Read and Write Drivers for Antiferromagnetic Tunnel Junction (AFMTJ) Memories
  Yousuf Choudhary and Tosiron Adegbija
  International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Hsinchu, Taiwan, April 2026
  

  Abstract

  Antiferromagnetic Tunnel Junctions (AFMTJs) offer picosecond switching and high integration density for in-memory computing, but their ultrafast dynamics and low tunnel magnetoresistance (TMR) make state-of-the-art MRAM interfaces unreliable. This work develops a device-circuit co-designed read/write interface optimized for AFMTJ behavior. Using a calibrated SPICE AFMTJ model as a baseline, we identify the limitations of conventional drivers and propose an asymmetric pulse driver (PD) for deterministic picosecond switching and a self-timed sense amplifier (STSA) with dynamic trip-point tuning for low-TMR sensing. Our experiments using SPICE and Monte Carlo evaluations demonstrate that the proposed circuits preserve AFMTJ latency and energy benefits while achieving robust read/write yield under realistic PVT and 3D integration parasitics, outperforming standard MRAM front-ends under the same conditions.

• Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study
  Yousuf Choudhary and Tosiron Adegbija
  Design Automation and Test in Europe (DATE), Verona, Italy, April 2026
  

  Abstract

  Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulation framework integrating multi-sublattice Landau-Lifshitz-Gilbert (LLG) dynamics with circuit-level modeling. SPICE-based simulations show that AFMTJs achieve ~8x lower write latency and ~9x lower write energy than conventional MTJs. When integrated into an in-memory computing architecture, AFMTJs deliver 17.5x average speedup and nearly 20x energy savings versus a CPU baseline—significantly outperforming MTJ-based IMC. These results establish AFMTJs as a compelling primitive for scalable, low-power computing.

2025

• Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture
  Ilkin Aliyev, Jesus Lopez, and Tosiron Adegbija
  Design Automation and Test in Europe (DATE), March 2025
  [Preprint]

2024

• An Open-Source Tool for Generating Domain-Specific Accelerators for Resource-Constrained Computing
  David T. Kerns and Tosiron Adegbija
  Journal of Open Source Software [PDF] [Github]

• System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints
  Yuchao Liao, Tosiron Adegbija, and Roman Lysecky
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024
  [Preprint]

• Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
  Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija, and Jean-Marc Fellous
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), December 2024
  [Preprint]

• (Invited Paper) Are LLMs Any Good for High-Level Synthesis?
  Yuchao Liao, Tosiron Adegbija, and Roman Lysecky
  ACM/IEEE International Conference on Computer-Aided Design (ICCAD), October 2024
  [Preprint]

• STT-RAM-based Hierarchical In-Memory Computing
  Dhruv Gajaria, Kevin Gomez, and Tosiron Adegbija
  IEEE Transactions on Parallel and Distributed Systems (TPDS), July 2024
  [Preprint]

• CHIME: Energy-Efficient STT-RAM-based Concurrent Hierarchical In-Memory Processing
  Dhruv Gajaria, Tosiron Adegbija, Kevin Gomez
  IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), July 2024
  [PDF]

• Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
  Yuchao Liao, Tosiron Adegbija, Roman Lysecky, and Ravi Tandon
  ACM Great Lakes Symposium on VLSI (GLSVLSI), June 2024
  [Preprint]

• Domain-Specific STT-MRAM-based In-Memory Computing: A Survey
  Alaba Yusuf, Tosiron Adegbija, and Dhruv Gajaria
  IEEE Access, February 2024
  [PDF]

• PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine
  Ilkin Aliyev and Tosiron Adegbija
  IEEE International Symposium on Circuits and Systems (ISCAS), May 2024
  [Preprint]

• Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks
  Ilkin Aliyev and Tosiron Adegbija
  Design Automation and Test in Europe (DATE) LBR, March 2024
  [Preprint]

2023

• Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators
  Ilkin Aliyev, Kama Svoboda, and Tosiron Adegbija
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), October 2023
  [PDF] [URL]

• jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research
  Tosiron Adegbija
  IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), June 2023
  [PDF] [Github]

• Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric authentication
  James Kuban and Tosiron Adegbija
  International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), April 2023
  [PDF]

• Efficient System-Level Design Space Exploration for High-Level Synthesis using Pareto-Optimal Subspace Pruning
  Yuchao Liao, Tosiron Adegbija, and Roman Lysecky
  Asia and South Pacific Design Automation Conference (ASP-DAC), January 2023
  [PDF]

2022

• A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy
  Dhruv Gajaria, Kevin Gomez, and Tosiron Adegbija
  IEEE International Conference on Computer Design (ICCD), October 2022
  [PDF]

• Evaluating the Performance and Energy of STT-RAM Caches for Real-World Wearable Workloads
  Dhruv Gajaria and Tosiron Adegbija
  Future Generation Computer Systems, 2022
  [PDF] [URL]

• A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation
  Kyle Kuan and Tosiron Adegbija
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2022
  [PDF]

• A High-Level Synthesis Approach for Precisely-Timed, Energy-Efficient Embedded Systems
  Yuchao Liao, Tosiron Adegbija, and Roman Lysecky
  ELSEVIER Sustainable Computing: Informatics and Systems (SUSCOM)/IEEE International Green and Sustainable Computing Conference (IGSCC21-Journal-Integrated Issue), 2022
  [PDF] [URL]

2021

• DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing
  Ankur Limaye and Tosiron Adegbija
  ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), July 2021
  [PDF]

• Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing
  Dhruv Gajaria and Tosiron Adegbija
  Springer Journal of Signal Processing Systems (JSPS), Special Issue on Signal Processing for Smart Sensors, Wearables, and IoTs, July 2021
  [PDF] [URL]

2020

• Energy Characterization of Graph Workloads
  Ankur Limaye, Antonino Tumeo, and Tosiron Adegbija
  ELSEVIER Sustainable Computing (SUSCOM)/IEEE International Green and Sustainable Computing Conference (IGSCC20-Journal-Integrated Issue), October 2020.
  [PDF] [URL] [DATA]

• A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches
  Kyle Kuan and Tosiron Adegbija
  IEEE International Conference on Computer Design (ICCD), October 2020.
  [PDF]

• ECG-based Authentication using Timing-Aware Domain-Specific Architecture
  Renato Cordeiro, Dhruv Gajaria, Ankur Limaye, Tosiron Adegbija, Nima Karimian, and Fatemeh Tehranipoor
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)/CODES+ISSS, September 2020
  [PDF] [URL]

• Biomimetic Middleware Design Principles for IoT Infrastructures
  Zenon Chaczko, Ryszard Klempous, Jerzy Rozenblit, Tosiron Adegbija, Christopher Chiu, Konrad Kluwak, and Czeslaw Smutnicki
  Acta Polytechnica Hungarica
  [PDF] [URL]

• CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side Channel Attacks
  Chenxi Dai and Tosiron Adegbija
  IEEE Consumer Electronics Magazine (CEM), April 2020
  [PDF] [URL]

2019

• Bit-wise and Multi-GPU Implementations of DNA Recombination Algorithm
  Elnaz Tavakoli Yazdi, Ankur Limaye, Ali Akoglu, Tosiron Adegbija, and Adam Buntzman
  IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC), Hyderabad, India, December 2019
  [PDF]

• Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures
  Kyle Kuan and Tosiron Adegbija
  International Green and Sustainable Computing Conference (IGSC), PhD Forum, Washington DC, October 2019
  [PDF]

• SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
  Dhruv Gajaria, Kyle Kuan, and Tosiron Adegbija
  International Green and Sustainable Computing Conference (IGSC), Washington DC, October 2019
  [PDF]

• ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
  Dhruv Gajaria and Tosiron Adegbija
  International Symposium on Memory Systems (MEMSYS), Washington DC, USA, October 2019
  [PDF]

• A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior
  Keeley Criswell and Tosiron Adegbija
  IEEE Transactions on Parallel and Distributed Systems (TPDS)
  [PDF] [URL]

• Energy and Performance Analysis of STTRAM Caches for Mobile Applications
  Kyle Kuan and Tosiron Adegbija
  IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, October 2019
  [PDF]

• HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
  Kyle Kuan and Tosiron Adegbija
  IEEE Transactions on Computers (TC)
  [PDF] [URL] [Modified GEM5]

• Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
  Kyle Kuan and Tosiron Adegbija
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  [PDF] [URL] [Modified GEM5]

• mirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache
  Kyle Kuan and Tosiron Adegbija
  ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington DC, USA, May 2019
  [PDF]

• Right-Provisioned IoT Edge Computing: An Overview
  Tosiron Adegbija, Roman Lysecky, and Vinu Vijay Kumar
  ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington DC, USA, May 2019
  [PDF]

• Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems
  Mohamad Hammam Alsafrjalani, Tosiron Adegbija, and Lokesh Ramamoorthi
  International Symposium on Quality Electronic Design (ISQED), Santa Clara CA, USA, March 2019.
  [PDF]

2018

• HERMIT: A Benchmark Suite for the Internet of Medical Things
  Ankur Limaye and Tosiron Adegbija
  IEEE Internet of Things Journal, 2018.
  [PDF] [Download benchmarks]

• Realizing Closed-loop, Online Tuning and Control for Configurable-cache Embedded Systems: Progress and Challenges
  Islam S. Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohammad. H. Alsafrjalani
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, July 2018.
  [PDF]

• TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems
  Mohamad Hammam Alsafrjalani and Tosiron Adegbija
  ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, May 2018.
  [PDF]

• A Workload Characterization of the SPEC CPU2017 Benchmark Suite
  Ankur Limaye and Tosiron Adegbija
  IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, Northern Ireland, UK, April 2018.
  [PDF] [SPEC CPU2017 Command Lines]

• LARS: Logically Adaptable Retention Time STT-RAM Cache for Embedded Systems
  Kyle Kuan and Tosiron Adegbija
  Design, Automation and Test in Europe (DATE), Dresden, Germany, March 2018.
  [PDF] [Modified GEM5]

• Modular Electronics for Broadening Non-Expert Participation in STEM Innovation: An IoT Perspective
  Nikitha Ramohalli and Tosiron Adegbija
  IEEE Integrated STEM Education Conference (ISEC), Princeton, NJ, March 2018.
  [PDF]

• AMELIA: An Application of the Internet of Things for Aviation Safety
  Jeremiah Pate and Tosiron Adegbija
  IEEE Consumer Communications and Networking Conference (CCNC), Las Vegas NV, USA, January 2018
  [PDF]

2017

• TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  MDPI Computers Journal Special Issue on Multi-Core Systems-On-Chips Design and Optimization, December 2017
  [PDF] [URL]

• PhLock: A Cache Energy Saving Technique Using Phase-based Cache Locking
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE Transactions on Very Large Scale Integration Systems (TVLSI), October 2017
  [PDF] [URL]

• Application-Specific Autonomic Cache Tuning for General Purpose GPUs
  Sam Gianelli, Edward Richter, Diego Jimenez, Hugo Valdez, Tosiron Adegbija, and Ali Akoglu
  IEEE International Conference on Cloud and Autonomic Computing (ICCAC), Tucson AZ, USA, September 2017
  [PDF]

• Microprocessor Optimizations for the Internet of Things: A Survey
  Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, and Ann Gordon-Ross
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Special Issue on Circuit and System Design Automation for the Internet of Things, June 2017
  [PDF] [URL]

• Exploiting Configurability as a Defense Against Cache Side Channel Attacks
  Chenxi Dai and Tosiron Adegbija
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017
  [PDF]

• A Workload Characterization for the Internet of Medical Things (IoMT)
  Ankur Limaye and Tosiron Adegbija
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017
  [PDF]

• PACT: Priority-Aware Phase-based Cache Tuning for Embedded Systems
  Sam Gianelli and Tosiron Adegbija
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017
  [PDF]

• Coding for Efficient Caching in Multicore Embedded Systems
  Tosiron Adegbija and Ravi Tandon
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, July 2017
  [PDF]

2016

• Phase-based Dynamic Instruction Window Optimization for Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh PA, USA, July 2016
  [PDF]

• Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems
  Tosiron Adegbija
  Great Lakes Symposium on VLSI (GLSVLSI), Boston MA, USA, May 2016
  [PDF]

2015 and prior

• Enabling Right-Provisioned Microprocessor Architectures for the Internet of Things
  Tosiron Adegbija, Anita Rogacs, Chandrakant Patel, and Ann Gordon-Ross
  ASME International Mechanical Engineering Congress and Exposition (IMECE), Houston TX, USA, November 2015
  [PDF]

• Phase-based Cache Locking for Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  ACM Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh PA, USA, May 2015
  [PDF]

• Analysis of Cache Tuner Architectural Layouts for Multicore Embedded Systems
  Tosiron Adegbija, Ann Gordon-Ross, and Marisha Rawlins
  IEEE International Performance Computing and Communications Conference (IPCCC), Austin TX, USA, December 2014
  [PDF]

• Dynamic Phase-based Optimization of Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa FL, USA, July 2014 - PhD Forum
  [PDF]
  Received Best Paper Award

• Thermal-aware Phase-based Tuning of Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  ACM Great Lakes Symposium on VLSI (GLSVLSI), Houston TX, USA, May 2014
  [PDF]

• Energy-efficient Phase-based Cache Tuning for Multimedia Applications in Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE Consumer Communications and Networking Conference (CCNC), Las Vegas NV, USA, January 2014
  [PDF]

• Phase Distance Mapping: A Phase-based Cache Tuning Methodology for Embedded Systems
  Tosiron Adegbija, Ann Gordon-Ross, and Arslan Munir
  Special Issue on Self-adaptive Networked Embedded Systems, Springer Design Automation for Embedded Systems (DAEM), January 2014
  [PDF] [URL]

• Exploiting Dynamic Phase Distance Mapping for Phase-based Tuning of Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE International Conference on Computer Design (ICCD), Asheville NC, USA, October 2013
  [PDF]

• Exploring the Tradeoffs of Heterogeneity and Configurability in Multicore Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IARIA International Conference on Mobile Ubiquitous Computing, Systems, Services and Technologies (UBICOMM), Porto, Portugal, October 2013
  [PDF]

• Dynamic Phase-based Tuning for Embedded Systems Using Phase Distance Mapping
  Tosiron Adegbija, Ann Gordon-Ross, and Arslan Munir
  IEEE International Conference on Computer Design (ICCD), Montreal, Canada, October 2012
  [PDF]

Poster Presentations

• Architectural Support for the Internet of Things
  Tosiron Adegbija, Anita Rogacs, and Chandrakant Patel
  Hewlett Packard Intern Project Fair, Palo Alto CA, USA, July 2014

• Dynamic Phase-based Optimization of Embedded Systems
  Tosiron Adegbija and Ann Gordon-Ross
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa FL, USA, July 2014 - PhD Forum